Scaling down of active device dimensions in the manufacture of integrated circuits (IC's) has improved circuit performance and increased the functional capability of the active devices packed on a semiconductor substrate. The full benefit of such advances in active-device density may be realized only if the active devices are effectively interconnected. As the active device density increases and feature sizes shrink, the signal-transmission effectiveness and efficiency of the interconnect structure eventually limit the circuit performance and functional capability of an IC chip.
Multi-level interconnect structures have been developed that match the advances in active-device density by more effectively routing metallization lines between the active devices. In certain IC designs, five or more individual levels of metallization lines may be required to accommodate the active-device density. Multilevel interconnect structures arrange the metallization lines in multiple layers in which the metallization lines of each individual level are formed in an interlevel dielectric. The interlevel dielectric electrically isolates the metallization lines from one another in each level of the interconnect structure and electrically isolates metallization lines in adjacent levels.
Damascene processes are routinely used in back-end-of-line (BEOL) processing for fabricating multilevel interconnect structures. In a damascene process, trenches and vias are etched in a layer of an interlevel dielectric and filled with metal, such as copper (Cu) or a Cu-based alloy, to create metallization lines and vertical conductive paths between metallization lines in different levels. Copper has superior electromigration resistance and lower resistivity than other candidate metals, such as aluminum, considered for fabricating multilevel interconnect structures. Traditional subtractive etching approaches cannot form copper metallization lines because copper is difficult to etch. Therefore, damascene processes are particularly meaningful for fabricating copper metallization lines.
In a dual-damascene process, the interlevel dielectric layer is conformally covered by a blanket of metal that simultaneously fills the trenches and vias. Excess overburden metal is removed from the interlevel dielectric by a process such as chemical-mechanical polishing (CMP). Metal remaining in the trenches extends substantially horizontal relative to the substrate to define metallization lines, and metal remaining in the vias provides contacts between metallization lines in adjacent levels. A single-damascene process forms trenches and vias in distinct interlevel dielectric layers and fills each with a distinct blanket deposition of metal.
As the active-device density increases and feature sizes shrink, the line-to-line spacings between adjacent, on-pitch metallization lines in individual layers and between metallization lines in adjacent layers of the multi-level interconnect structure are reduced. Shrinking the line-to-line spacings increases the line-to-line capacitance, which slows the speed of the signals carried by the metallization lines and results in propagation delay.
Reducing the dielectric constant of the interlevel dielectric reduces the line-to-line capacitance. To that end, one trend in multilevel interconnect structures is to form the interlevel dielectric from a dielectric material characterized by a relative permittivity or dielectric constant less than the dielectric constant of silicon oxide or fluorinated silicon glass. Generally, such low-k dielectrics are characterized by a dielectric constant less than about four, which represents the dielectric constant of silicon oxide. Candidate low-k materials include spin-on low-k films, such as SILK commercially available from Dow Chemical Co. (Midland, Mich.), and chemical vapor deposition low-k films, such as organosilicates. The reduction in line-to-line capacitance afforded by low-k dielectrics permits adjacent metallization lines to be positioned closer together and thereby enable more effective circuit wiring for a given number of interconnect levels.
Damascene processes place stringent requirements on the properties of the material forming interlevel dielectric layer and, hence, on the candidate low-k dielectrics projected for use as an interlevel dielectric. The numerous requirements have limited the integration of low-k dielectrics into damascene processes for fabrication multilevel interconnect structures. In particular, low-k dielectrics must be compatible with the cleaning, etching, CMP and thermal treatments characteristic of a damascene manufacturing process. The low-k dielectric must have sufficient mechanical strength and chemical stability to withstand all the manufacturing processes.
An extremely low-k dielectric for forming multilevel interconnect structure is air, which has a dielectric constant of about unity. Mechanical strength is lent during processing by incorporating a removable or sacrificial material as a temporary interlevel dielectric and removing the sacrificial material after the levels of the multilevel interconnect structure are completed. The spaces formerly occupied by the sacrificial material are filled with air to form a freestanding latticework of metallization. Despite its attractiveness as a low-k dielectric, air lacks structural rigidity.
Multi-level interconnect structures include bond pads that represent relatively large metal areas distributed about the device side of the substrate. Bond pads are used to establish electrical contact between the integrated circuits and either a package or a probe pin. A probe is an instrument that makes an electrical contact of a probe pin with the bond pads so voltage or current can be applied to test for device functionality. Contact between the probe pin and bond pad can damage the metallization and interlevel dielectric of the underlying levels of an air-filled interconnect structure. For example, the probe pin can apply a vertical force to the bond pad of a magnitude that can crush or partially collapse the interconnect structure as the metallization itself lacks the strength to successfully resist the vertical force. The resulting damage compromises the quality of the interconnect structure and may create electrical shorts between metallization lines in adjacent levels.
Wire bonders attach small diameter bonding wires between the bond pads and a sealed package that provide a lead system for connecting the active devices to a printed circuit board or any other desired suitable external circuitry. The package also protects the IC from damage and from contaminants in the surrounding environment. The wire bonding process can cause damage to the underlying interconnect levels because the air-filled spaces surrounding the metallization lack mechanical strength.
A conventional approach for reinforcing the interconnect structure is to introduce a dense array or “sea” of metal-filled vias in one or more interconnect levels beneath each bonding pad or probe pad. To afford effective rigidity, the vias are vertically aligned beneath the bond pad and are present in several levels of the interconnect structure. However, the vias significantly restrict use of the space beneath the bond pad for metallization coupling active devices. In addition, allowed via densities in IC designs limit the potential strengthening effect. Therefore, this conventional approach has significant deficiencies.
What is needed, therefore, is a method and structure to reinforce bond pads in multilevel interconnect structures against a vertical force, such as is applied during probing and wirebonding.